1. Field of the Invention
The present invention relates generally to binary data generating circuits and A/D converters, and more particularly, to a binary data generating circuit and an A/D converter which is less susceptible to noise. The present invention has particular applicability to a parallel-type and a serial-parallel type A/D converters.
2. Description of the Background Art
Conventionally, a converter which converts an analog signal to a digital signal (hereinafter "A/D converter") is widely used for performing digital signal processing with respect to an analog signal. High-speed conversion is also required in A/D converters, since high-speed digital signal processing is required, for example, in the field of video signal processing.
As A/D converters suitable for high-speed conversion, parallel-type and serial-parallel type A/D converters have been known conventionally. These A/D converters employ many comparators and generally, power consumption of A/D converter is approximately determined by the number of the comparators used. In any parallel-type and serial-parallel type A/D converters, the analog input signal is applied to the inputs of a plurality of comparators in parallel. In addition, in serial-parallel type A/D converter, the conversion of an analog signal to a digital signal is performed in series on time axis.
The parallel-type A/D converter is operable at high-speed. However, since it needs many more comparators than those needed by the serial-parallel type A/D converter, power consumption is greater and therefore often used for industrial or electronic machines for service, such as oscilloscope or the like. The serial-parallel type A/D converter is slower than the parallel-type converter. However, since it has small power consumption and can be formed within a small occupied region on a semiconductor substrate, that is to say, suitable for integration, it is often used in consumer products for the private sector. The present invention is applicable to both the parallel-type A/D converter and the serial-parallel type A/D converter.
FIG. 14 is a block diagram showing a general configuration for video signal processing. With reference to FIG. 14, an object not shown is imaged by a video camera 91. Since the video signal provided from video camera 91 is analog, it is converted to the digital video signal by an A/D converter 92. The digital video signal is applied to a digital video signal processing circuit 93, which performs digital signal processing of the video signal. Processed data is applied to a D/A converter 94 and converted to the analog signal therein. The processed analog signal provided from D/A converter 94 is applied to a display unit 95 and a processed image is represented on the screen provided therein (not shown). The foregoing parallel-type or serial-parallel type A/D converter is applicable to A/D converter 92 shown in FIG. 14.
FIG. 15 is a circuit block diagram of a conventional parallel-type A/D converter. The A/D converter shown in FIG. 15 is disclosed in the article entitled "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter", IEEE Journal of SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, pp. 926-931, Dec., 1979, by ANDREW G. F. DINGWALL. For simplicity of description, the A/D converter providing 3-bit digital data is illustrated in FIG. 15.
Referring to FIG. 15, an A/D converter includes a ladder resistance circuit 1 provided with resistors 60 to 70 connected in series between the externally applied reference potentials Vrel and Vre2, a comparator circuit 4 provided with seven comparators C0 to C6, a pre-encoder 2 provided with 8 AND gates A0 to A7 and an encoder 3 connected to the outputs of pre-encoder 2. Since ladder resistance circuit 1 is provided with resistors 60 to 67 each having the same resistance value, it generates seven reference voltages V0 to V6 determined by the resistance division. Seven reference voltages V0 to V6 are applied to comparators C0 to C6 provided within comparator circuit 4, respectively.
Each of the comparators C0 to C6 provided within comparator circuit 4 compares an analog signal with corresponding one reference voltage to provide 7-bit data (referred to as "thermometer code") which indicates a comparison result. Each bit of thermometer code is applied to respective two adjacent AND gates provided in pre-encoder 2.
Each of AND gates A0 to A7 in pre-encoder 2 has two inputs, one input thereof constituting an inversion input and being connected from an inverter. For example, the j-th AND gate Aj has its inversion input connected to the output of the j-1st comparator Cj-1 and its non-inversion input connected to the output of the j-th comparator Cj. The inversion input of AND gate A0 is grounded and the non-inversion input of AND gate A7 is connected to a power supply potential Vcc. Output signals j0 to j7 provided from AND gates A0 to A7 are applied to encoder 3, where the signals are converted to corresponding binary data B0 to B2.
FIG. 16 is a schematic diagram of a circuit of encoder 3 shown in FIG. 15. As shown in FIG. 16, encoder is implemented by a pseudo NMOS type read-only memory (hereinafter "ROM") to generate a straight binary code. This encoder 3 includes NMOS transistors, selectively turned on responsive to input signals J0 to J6 applied from pre-encoder 2 and PMOS transistors which are turned on by applying a bias voltage V.sub.B1 thereto. In normal operation, as one of the input signals J0 to J7 is at a high level (data "1"), only NMOS transistor supplied with high level input is turned on. As a result, binary data B0 to B2 corresponding to the input signals J0 to J7 are provided. A relationship between input signals J0 to J7 and binary data B0 to B2 is shown in the following Table 1.
TABLE 1 ______________________________________ B.sub.2 B.sub.1 B.sub.0 ______________________________________ J.sub.7 111 J.sub.6 110 J.sub.5 101 J.sub.4 100 J.sub.3 011 J.sub.2 010 J.sub.1 001 J.sub.0 000 ______________________________________
Since encoder 3 shown in FIG. 16 is of pseudo-NMOS type, current driving ability or load driving ability (corresponding to mutual conductance gm) of PMOS transistors in encoder 3 is indicated to be smaller than that of NMOS transistors. Therefore, only the transistor supplied with high level input is turned on, so that the potentials of bit lines BL0 to BL2 become selectively lowered. As a result, binary output data B0 to B2 are obtained through bit lines BL0 to BL2.
Therefore, in normal operation, when only any one of input signals J0 to J7 is at a high level (i.e., data "1"), binary data B0 to B2 shown in Table 1 are provided from encoder 3. Referring to Table 1, when only the input signal J3 is at a high level, for example, encoder 3 shown in FIG. 16 provides (0, 1, 1) as output data (B2, Bl, B0).
Now, the entire operation of A/D converter 5a shown in FIG. 15 will be explained. Predetermined reference voltages Vre1 and Vre2 are applied to a ladder resistance circuit 1. Reference voltages Vre1 and Vre2, in case that this A/D converter 5a is employed as A/D converter 92 shown in FIG. 14, for example, are determined by changeable maximum and minimum potentials of the video signal being input. Ladder resistance circuit 1 divides the voltage difference Vrel-Vre2 by eight resistors 60 to 67 to generate seven reference voltages V0 to V6. Seven reference voltages are applied to comparators C0 to C6 in comparator circuit 4, respectively. Each of the comparators C0 to C6 compares an applied reference voltage with the voltage of an analog input signal to provide data "1" when the analog signal voltage is larger than the reference voltage. On the other hand, when the analog signal voltage is smaller than the reference voltage, data "0" is provided.
FIG. 17 is a signal transition diagram showing the operation of encoder 3 of FIG. 15. With reference to FIG. 17, when potential Vin of analog input signal Si lies between the voltages V3 and V4, comparators C0 to C3 provide data "1". On the other hand, each of comparators C4 to C6 provides data "0", respectively. Therefore, comparator circuit 4 of FIG. 15 provides a thermometer code TC shown in FIG. 17.
Two gates, adjacent to each other, of AND gates A0 to A7 in pre-encoder 2 each receives one corresponding data in thermometer code TC1. Among AND gates A0 to A7, only AND gate A4 that receives data "0" and "1" provides data "1". Other AND gates A0 to A3 and A5 to A7 provide data "0". Therefore, output signals J0 to J7 are provided from pre-encoder 2, in which only signal J4 is "1". Encoder 3, therefore, provides binary output data (B2, Bl, B0) =(1, 0, 0) based on Table 1 described above.
The foregoing is a description of the case where A/D converter 5a shown in FIG. 15 operates normally; however, A/D converter 5a is affected by noise or the like, causing frequent malfunction as set forth in the following. First, the factor which causes noise in A/D converter 5a will be described hereinafter.
Referring to FIG. 28, it is assumed that some noise source NS exists in semiconductor substrate 5. In addition, it is also assumed that comparators C0 to C6 are located close to noise source NS on substrate 5 as shown in FIG. 28. Noise overlapped in inner circuits of comparators C0 to C6 becomes larger in the comparator closer to the noise source; however, the comparison result brought to the comparator having smaller difference between analog input signal Si and an applied reference voltage is more susceptible to noise. Accordingly, in the example shown in FIG. 28, comparators C0 and C1 are more susceptible to noise than comparators C3 and C4.
Referring to FIG. 29, it is assumed that signal Si is sampled at a time t2 after the sampling of analog input signal Si at a time t1. Preferably, only the output signal of comparator C0 should be changed from "1" to "0" by the sampling at the time t2; however, such a malfunction as in the following is caused by noise.
As shown in FIG. 30A, it is assumed that waveforms of the output signals of comparators C0 to C6 are changed by noise. At the time t2, in the case where comparators C0 to C6 operate at a time t4 after the sampling of input signal Si at the time t2, comparators C0 to C6 and AND gates A0 to A7 provide output signals as shown in FIG. 30B. That is, since output signals of comparators C0 to C6 are not affected by noise at the time t4, preferable comparison result can be obtained.
Conversely, in the case where comparators C0 to C6 operate at a time t3, comparator C1 erroneously provides "1" as shown in FIG. 30C, causing AND gates A0 and A2 to provide output signals J0 and J2 of "1". That is, pre-encoder 2 provides abnormal output signals J0 to J7, and this abnormal condition is referred to as "multi-addressing".
FIG. 18 is a signal transition diagram for illustrating an abnormal operation of encoder 3 shown in FIG. 15. Comparator 4 shown in FIG. 15 may provide a wrong thermometer code TC2 shown in FIG. 18 by an influence of noise or the like. That is, comparator C3 provides data "0", though it should provide data "1". In addition to this, comparator C4 provides data "1", though it should provide data "0". That is, an abnormal condition referred to as "multi-addressing" is occurring. Since abnormal thermometer code TC2 is applied to pre-encoder 2, as a result, AND gates A3 and A5 in pre-encoder 2 provide data "1". Therefore, as output signals J0 to J7 are provided, in which only signals J3 and J5 are "1", encoder 3 provides binary data, (B2, B1, B0) =(0, 0, 1).
The reason why the binary output data (0, 0, 1) can be obtained will be explained as follows. As shown in FIG. 18, binary output data is (0, 1, 1), when only signal J3 is data "1". On the other hand, binary output data is (1, 0, 1), when only signal J5 is "1". As encoder 3 has such a circuit configuration as shown in FIG. 16, that is, pseudo-NMOS type ROM, a logical product of corresponding bits of two pieces of data (0, 1, 1) and (1, 0, 1), that is "AND" data (0, 0, 1) is provided as binary output data.
In the example described above, binary output data (1, 0, 0) is provided in normal operation as shown in FIG. 17; however, in a wrong operation, binary output data (0, 0, 1) is obtained as shown in FIG. 18. Since a difference between normal data (1, 0, 0) and abnormal data (0, 0, 1) is 4LSB, it can be seen that binary output data having a large abnormal value by the generation of multi-addressing is provided.
Therefore, in a case where A/D converter 5a of FIG. 15 is applied to A/D converter 92 shown in FIG. 14, the binary output data having a large abnormal value is applied to the digital video signal processing circuit 93, and an abnormal image will be represented on the screen of display unit 95.
In the foregoing description, an explanation of a parallel-type A/D converter has been given, and a similar abnormal operation also occurs in a serial-parallel type A/D converter. This will be described hereinafter.
FIG. 19 is a circuit block diagram of a conventional serial-parallel type A/D converter. A/D converter 5b shown in FIG. 19 can be seen in the article entitled "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE Journal of SOLID-STATE CIRCUITS, VOL. SC-20, No. 6, pp. 1138-1143, Dec. 1985, by ANDREW G. F. DINGWALL.
Referring to FIG. 19, serial-parallel type A/D converter 5b includes a reference voltage generating circuit 11 which receives externally applied reference voltages Vre1 and Vre2 to generate the reference voltages of various levels. Reference voltage generating circuit 11 generates reference voltages for more significant bits F0 to F6 and reference voltages for less significant bits H0 to H12 in response to control signals J0 to J7, applying them to a more significant comparator 13 and a less significant comparator 14, respectively. In A/D converter 5b of FIG. 19, as an example, A/D conversion of 6 bits in total including 3 more significant bits and 3 less significant bits is performed. Therefore, more significant comparator 13 receives seven reference voltages for more significant bits F0 to F6 from reference voltage generating circuit 11. On the other hand, less significant comparator 14 receives 13 (=7+6) reference voltages for less significant bits H0 to H12 in order to perform .+-.3LSB error correction as will be described hereinafter.
More significant comparator circuit 13 has a circuit configuration similar to that of comparator circuit 4 shown in FIG. 15, and thus is provided with seven comparators (not shown) operating similarly. Seven output signals provided from more significant comparator circuit 13 are applied to a more significant pre-encoder 15.
More significant pre-encoder 15 also has a circuit configuration similar to that of pre-encoder 2 shown in FIG. 15, and operates similarly. Eight output signals provided from more significant pre-encoder 15 are applied to a more significant encoder 16. More significant encoder 16 also has a circuit configuration similar to that of encoder 3 shown in FIG. 16, and operates similarly. Therefore, binary output data of more significant bits B3 to B5 are provided from more significant encoder 16 and applied to an error correction circuit 19.
Less significant comparator circuit 14 also has a circuit configuration similar to that of more significant comparator circuit 13. That is, less significant comparator 14 is provided with 13 comparators (not shown) for comparing analog input signal Si with 13 reference voltages H0 to H12 applied from reference voltage generating circuit 11, respectively.
Output signals provided from less significant comparator circuit 14 are applied to a less significant pre-encoder 17. Less significant pre-encoder 17 also has a circuit configuration similar to that of more significant pre-encoder 15, and operates similarly. Output signals provided from less significant pre-encoder 17 are applied to a less significant pre-encoder 18. Less significant pre-encoder 18 also has a circuit configuration similar to that of more significant pre-encoder 16 and operates similarly.
Less significant encoder 18 provides output signals OS, US and B0 to B2 of 5 bits in total. Among these output signals, data indicating the result of the A/D conversion of less significant bits are less significant 3 bits B0 to B2. An overscale signal OS of the most significant bit is applied to error correction circuit 19. An underscale signal US of the second from the most significant bit is applied to error correction circuits 19 and 20. Therefore, error correction circuit 19 receives binary data of more significant bits B3 to B5 and signals OS and US to provide error correction codes E3 to E6. Error correction circuit 20 receives binary data of less significant bits B0 to B2, error correction codes E3 to E6 and signal US to provide binary output data D0 to D5 having the errors corrected.
FIG. 31 is a schematic diagram of less significant comparator 14, less significant pre-encoder 17 and less significant encoder 18 shown in FIG. 19.
FIG. 20 is a schematic diagram of a reference voltage generating circuit 11 shown in FIG. 19. Referring to FIG. 20, this reference voltage generating circuit 11 includes seven ladder resistance circuits 110 to 117 and seven switching circuits 100 to 107 each connected to the outputs of ladder circuits 110 to 117, respectively. Since this reference voltage generating circuit 11 is used for A/D conversion of 6 bits, a total of the 6th power of 2 resistance elements 6 are provided within ladder circuits 110 to 117. Each of ladder resistance circuits 110 to 117 is provided with eight resistance elements 6. For example, the j-th ladder resistance circuit 11j is provided with eight resistance elements 6 connected in series.
Each of switching circuits 100 to 107 connected to the outputs of each of ladder resistance circuits 110 to 117 is provided with thirteen switching elements in total. For example, the j-th switching circuit 10j is provided with thirteen switching elements and these are turned on when the j-th signal Jj of the output signals J0 to J7 provided from more significant pre-encoder 15 shown in FIG. 19 is at a high level.
One terminal of each of switching elements SW0 to SW12 is connected to thirteen comparators (not shown) provided within less significant comparator circuit 14 through the output lines H0 to H12 of reference voltages for less significant bits, respectively. The other terminal of each of switching elements SW3 to SW9 is connected to the connection nodes corresponding to two resistors, adjacent to each other, in ladder resistance circuit 11j. The other terminal of each of switching elements SW0, SW1, SW10 and SW11 is connected to the corresponding connection nodes *1 to *4, respectively as shown in FIG. 20. The output lines F0 to F6 of reference voltages for more significant bits are connected to seven comparators (not shown) provided in more significant comparator 13, respectively.
Generally, the reference voltage generating circuit is designed to generate various difference voltages according to the necessity in the device to which A/D converter is applicable. A/D converters 5a and 5b shown in FIGS. 15 and 19 are often employed in a video signal processing circuit in which high-speed operation is required. In the field of video signal processing, an A/D converter having a conversion rate of approximately 20 MHz, resolution of 8 to 10 bits and full scale voltage of 1.0 or 2.0 V is generally required.
For example, in the A/D converter having resolution of 8 bits and full scale voltage of 1.0 V is split into the reference voltages of 256 levels and the difference of the split voltage between two corresponds to the quantization width. Quantization width is represented by the unit "LSB". In the example described above, 1LSB corresponds to approximately 40 mVn. When A/D conversion of 8 bits is performed by the serial-parallel type A/D converter for more significant 4 bits and less significant 4 bits, the quantization width of less significant A/D conversion is ILSB (=about 4 mV), and the quantization width of more significant A/D conversion is 16 LSB (=about 64 mV).
FIG. 21 is a circuit block diagram illustrating the error correction circuit 19 shown in FIG. 19. Referring to FIG. 21, error correction circuit 19 includes OR gate 190 having 2 inputs, and full adders 193 to 196 each having 2 inputs. Respective input terminals A of full adders 193 to 195 receive binary data of more significant bits B3 to B5 provided from more significant encoder 16. Input terminal A of full adder 196 is grounded. OR gate 190 receives underscale signal US and overscale signal 0S applied from lower encoder 18. The output signal of 0R gate 190 is applied to an input terminal B of full adder 193. Respective input terminals B of full adders 194 to 196 receive underscale signal US. Respective carry output terminals and carry input terminals, adjacent to one another, of full adders 193 to 196 are connected in pairs. Error correction codes E3 to E6 are provided, respectively, through sum output terminals SUM of full adders 193 to 196.
FIG. 22 is a block diagram of the error correction circuit 20 shown in FIG. 19. Referring to FIG. 22, error correction circuit 20 includes six switching circuits 210 to 215, inverter 201 and AND gates 202 and 203. Each of the switching circuits 210 to 215 is provided with three switching elements 25 to 27. Inverter 201 receives error correction code E6 to apply inverted signal to each of switching elements 25. AND gate 202 receives error correction code E6 and inverted underscale signal US to apply an output signal to each of switching elements 26. AND gate 203 receives error correction code E6 and underscale signal US to apply an output signal UFW to each of switching elements 27. Switching elements 25 to 27 in switching circuits 210 to 215 turn on or off in response to the output signals provided from inverter 201, AND gates 202 and 203.
One end of each of respective switching elements 25 in switching circuits 210 to 215 receives each of error correction codes E0 to E5. One end of each of respective switching elements 26 is connected to the power supply potential Vcc. One end of each of respective switching elements 27 is connected to a ground potential. The other end of each of three switching elements provided in each of switching circuits 210 to 215 is connected to data output terminals D0 to D5, respectively. Respective switching elements 25 to 27 turn on when applied control signals are high.
Now, the operation of conventional serial-parallel type A/D converter 5b will be explained. Serial-parallel type A/D converter 5b operates in two stages. In the first stage, more significant comparator circuit 13, more significant pre-encoder 15 and more significant encoder 16 operate similarly to comparator circuit 4, pre-encoder 2 and encoder 3 in FIG. 15. That is, the operation similar to that shown in FIG. 17 is performed in circuits 13, 15 and 16. Consequently, more significant encoder 16 provides binary output data of more significant bits B3 to B5 to apply them to error correction circuit 19. Eight output signals J0 to J7 of more significant pre-encoder 15 are also applied to reference voltage generating circuit 11.
In the second stage, reference voltage generating circuit 11 is operated in response to the control signals J0 to J7. Referring to FIG. 20, when the j-th control signal Jj is "1", for example, all switching elements SW0 to SW12 in switching circuit 10j turn on. The fact that the j-th output signal of more significant pre-encoder 15 is "1" means that the potential of analog input signal Si is larger than the reference voltage for more significant bits Fj-1 and smaller than the reference voltage for more significant bits Fj. Therefore, the potential of analog input signal Si is determined in more detail between the reference voltages Fj-1 and Fj by less significant comparator circuit 14 and subsequent circuits.
However, between the A/D conversions of more significant bits and less significant bits, inconsistency in the output data often occurs in the result of A/D conversions of more significant bits and less significant bits by the difference of the characteristics in circuits. To solve these problems, in A/D conversion of less significant bits, conversion within its broader voltage region including applied reference voltages Fj-1 and Fj is performed. That is, in the example shown in FIG. 20, a margin of .+-.3 LSB including reference voltages Fj-1 and Fj is allowed. One LSB is an input voltage corresponding to 1-bit data "1" provided from A/D converter, and is equal to the difference of the voltages applied to both ends of resistance elements 6 shown in FIG. 20.
Thirteen comparators (not shown) provided in less significant comparator circuit 14 compare analog input signal Si with each of the reference voltages for less significant bits H0 to H12, respectively. Output signals representing a comparison result (thermometer code) are applied to less significant pre-encoder 17. Less significant pre-encoder 17 is responsive to applied thermometer code to provide fourteen output signals J0 to J13 with only one signal showing data "1". Less significant encoder 18 receives output signals J0 to J13, responsive to one signal showing data "1", to provide binary data of less significant bits B0 to B2, overscale signal OS and underscale signal US.
Encoder 18 provides binary data (US, OS, B2, B1, B0) shown in the following Table 2 in normal operation in response to the applied signals J0 to J13.
TABLE 2 ______________________________________ US, OS, B.sub.2, B.sub.1, B.sub.0 US', OS', B.sub.2 ', B.sub.1 ', B.sub.0 ' ______________________________________ J.sub.13 01010 01010 J.sub.12 01001 01000 J.sub.11 01000 00001 J.sub.10 00111 00000 J.sub.9 00110 00101 J.sub.8 00101 00100 J.sub.7 00100 00001 J.sub.6 00011 00000 J.sub.5 00010 00001 J.sub.4 00001 00000 J.sub.3 00000 00001 J.sub.2 10111 00000 J.sub.1 10110 10101 J.sub.0 10101 10101 ______________________________________
When this A/D converter 5b operates normally, only one of the signals J3 to J10 shows data "1". In comparison between analog input signal Si and the reference voltages for less significant bits H0 to H12, when the potential of analog input signal Si is outside of the region detected in A/D conversion of more significant bits, and is a lower voltage (referred to as "underscale"), one of the signals J0 to J2 shows data "1". On the other hand, when the potential of analog input signal Si is outside of the region detected in A/D conversion of more significant bits, and is a higher voltage (referred to as "overscale"), one of the signals J11 to J13 shows data "1".
When underscale is caused, in addition-subtraction in A/D conversion of more significant bits, the fact is utilized that the most significant bit is "1". When overscale is caused, by utilizing the fact that the second from the most significant bit is data "1", the addition-subtraction is performed in A/D conversion of more significant bits. At this stage, the signal of the most significant bit acts as underscale signal US, while the signal of the second from the most significant bit acts as overscale signal OS.
Error correction circuit 19 operates as an arithmetic unit performing an addition or a subtraction of data "1" to or from the resulting data of A/D conversion of more significant bits on the occurrence of overscale or underscale in A/D conversion of less significant bits. As shown in FIG. 21, error correction circuit 19 applies data (1, 0, 0, 0) to full adders 193 to 196 on the occurrence of overscale, and applies data (1, 1, 1, 1) on the occurrence of underscale. In case where no overscale and underscale happens, data (0, 0, 0, 0) is applied to full adders 193 to 196, and therefore the resulting data of A/D conversion of more significant bits are provided as data E3 to E6 without any change.
Referring to FIG. 22, in error correction circuit 20, an error is corrected on the occurrence of overflow or underflow. When the potential of analog input signal Si is larger than the reference voltage Vrel, overflow occurs. On the other hand, when the potential of analog input signal Si is smaller than the reference voltage Vre2, underflow occurs. The occurrence of overflow is detected when data (1, 1, 1) is provided as a result of A/D conversion of more significant 3 bits and overscale signal OS is "1". The occurrence of underflow is detected when data (0, 0, 0) is provided as a result of A/D conversion of more significant 3 bits and underscale signal US is "1".
In case of overflow, all bits of the output data of A/D converter are preferably "1". When underflow occurs, all bits of the output data of A/D converter are preferably "0". However, on the occurrence of overflow, less significant 3 bits of the output data of error correction circuit 19 is the sum of data (1, 1, 1) and (0, 0, 1), i.e., data (0, 0, 0). In case of underflow, less significant 3 bits of the output data of error correction circuit 19 is the sum of data (0, 0, 0) and (1, 1, 1), i.e., (1, 1, 1). Therefore, error correction circuit 20 is provided so that A/D converter 5b may provide preferable output data on the occurrence of overflow and underflow.
An error correction function in error correction circuit 20 utilizes the fact that signal E6 becomes "1" just in case overflow or underflow occurs in error correction circuit 19. That is, underflow signal UFW is obtained by a logical product (AND gate 203) of signal E6 and underscale signal US. Overflow signal OFW is obtained by a logical product (AND gate 202) of signal E6 and inverted underscale signal US. If neither overflow nor underflow does occur, since respective switching elements 25 in switching circuits 201 to 205 turn on, data E0 to E5 are provided as final output data D0 to D5.
The operation of serial-parallel type A/D converter 5b shown in FIG. 19 has been explained in the foregoing description; however, as the operation for A/D conversion is basically the same as that for parallel-type A/D converter 5a shown in FIG. 15, the foregoing problem of multi-addressing is also occurring in A/D converter 5b. As an example of the occurrence of multi-addressing, wrong output data (US', OS', B2', B1', B0') provided from encoder 18 are shown in the foregoing Table 2. The left side column of Table 2 shows data to be provided in normal operation. By comparing the corresponding data in Table 2, respectively, a big difference caused by the occurrence of multi-addressing can been seen. In addition to this, despite of the occurrence of underscale or overscale, it is pointed out that the case where signal US or OS of "1" can not be obtained may occur.
As described above, multi-addressing has often occurred in conventional parallel-type A/D converter 5a and serial-parallel type A/D converter 5b with data widely different from desired output data has been provided. Any noise or delay in the transmission of the applied clock signal is believed to cause the generation of multi-addressing. In addition to this, malfunction of the comparator in comparator circuit or the output timing gap in an encoder is also taken into account. However, as the occurrence of multi-addressing could not be prevented completely, a big error in the output data caused by multi-addressing has not been prevented.